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12- bit deep color with quad hdmi receiver data sheet adv7614 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered tra demarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features ultralow jitter digital pll 4:1 m ultiplexed hdmi receiver hdmi 1.3 a support 36- /30 - /24 - bit deep color support flexible audio interface ( dsd, dst, dolby ? truehd, dts ?- hd master audio, and dts - hd high resolution audio) 225 mhz hdmi receiver hdmi re peater support high - bandwidth digital content protection (hdcp 1.3) programmable/adaptive equalizer for cable lengths up to 30 meters internal edid ram edid with hdmi cable power support cec support on - board audio mute controller general highly flexible ou tput interface 12- /10 - /8 - bit 4:4:4 or 12 - /10 - /8 - bit 4:2:2 pixel output interface stdi function support standard identification a ny - to - any 3 3 color space conversion matrixes free -r un t ime g enerator 2 programmable interrupt request output pins color c ontr ols low stand by power applications advanced tv s avr video receivers pdp hdtvs lcd tvs (hdtv ready) oled hdtvs lcd/dlp front projectors hdmi s witchers general description the adv7614 is a high quality, single - chip integrated 4:1 multiplexed high - definition multimedia interface (hdmi ? ) receiver. the adv7614 incorporates a quad input hdmi rec e iver tha t supports all hdtv formats up to 1080p and disp lay s resolutions up to uxga (1600 1200 at 60 hz). the reception of encrypted video is possible with the inclusion of hdcp. the hdmi receiver also includes programmable/adaptive equaliza tion that ensures robust operation of the interface wi th cable lengths up to 30 meters. the adv7614 provides complete audio support for eight chan - nels of i 2 s audio, sony/philips digital interface format ( s/pdif ) digital audio output, and super au dio cd ( sacd ) and com - pressed sacd support with d irect s tream d igital (dsd) and d irect s tream t ransfer (dst) output interfaces, respectively. the hdmi receiver also supports h igh b it r ate (hbr) audio streaming to allow recovery (and downstream processing) of compressed lossless audio formats, including dolby ? true hd and dts ?- hd m aster a udio or dts - hd h igh r esolution a udio. in addition, it also provides an advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. fabricated in an advanced cmos process, the adv7614 is provided in a space - saving, 260 - ball 15 mm 15 mm csp_bga surface - mount, rohs - compliant package. the adv7614 is specified over the ?40c to +70c temperature range .
adv7614 data sheet rev. c | page 2 of 20 table of contents features ........................................................................................... 1 applications ................................................................................... 1 general description ...................................................................... 1 revision history ............................................................................ 2 funct ional block diagram ............................................................ 3 specifications ................................................................................. 4 analog, digital, hdmi, and ac specifications ...................... 4 data and i 2 c timing characteristics ....................................... 5 power specifications .................................................................. 6 absolute maximum ratings ......................................................... 8 package thermal performance ................................................. 8 es d ca u t io n ............................................................................... 8 pin configuration and function descrip t io n s ............................ 9 functional overview ................................................................... 16 hdmi receiver ........................................................................ 16 component proces sor (cp) .................................................... 16 cp pixel data output modes .................................................. 16 i 2 c inte rface ............................................................................. 16 other features .......................................................................... 16 outline dimensions .................................................................... 17 ordering guide ........................................................................ 17 revision history 9/ 13 revision c : initial ve rsi o n
data sheet adv7614 rev. c | page 3 of 20 functional block diagram sync processing and clock generation scl sda cec cec controller control interface i 2 c hs, vs control and data control p0 to p11 p12 to p23 p24 to p35 llc int1 int2 hs vs _ field de mux rxa_c rxb_c rxc_c pll equalizer sampler hdmi processor edid repeater controller hdcp engine hdcp eeprom packet processor ddcb_sda ddcb_scl ddcc_sda ddcc_scl ddcd_sda ddcd_scl rxa_5v rxb_5v rxc_5v rxd_5v ep_miso ep_mosi ep_cs ep_sck shared_edid packet / infoframe memory lrclk/dsd2b/dst_ff sclk/dst_clk s/pdif/dsd0a/dst rxa_0 rxa_1 rxa_2 equalizer equalizer equalizer sampler rxb_0 rxb_1 rxb_2 sampler rxc_0 rxc_1 rxc_2 sampler rxd_0 rxd_1 rxd_2 data preprocessor and color space converter a b c llc ddca_sda ddca_scl 12 12 12 back end csc rxd_c i 2 s0/dsd0b/hbr0 i 2 s1/dsd1a/hbr1 i 2 s2/dsd1b/hbr2 i 2 s3/dsd2a/hbr3 output formatter component processor adv7614 mclkout audio 08186-001 pwrdn 36 figure 1.
adv7614 data sheet rev. c | page 4 of 20 s pecifications dvdd = 1.8 v 5%, dvddio = 3.3 v 5%, pvdd = 1.8 v 5%, tvdd = 3.3 v 5%, cvdd = 1.8 v 5%, t min to t max = ?40c to +70c , unless otherwise noted . analog, digital, hdm i, and ac specificat ions table 1 . parameter test conditions/comments min typ max unit digital input s input high voltage (v ih ) 2 v input low voltage (v il ) 0.8 v input current (i in ) reset pin ?60 +60 a other d igital input s ?10 +10 a input capacitance (c in ) 10 pf digital input s (5 v tolerant ) 1 input high voltage (v ih ) 2.6 v input low voltage (v il ) 0.8 v input c urrent (i in ) shared_edid pin ?150 +60 a other 5 v d igital input s ?82 +82 a digital output s output high voltage (v oh ) 2.4 v output low voltage (v ol ) 0.4 v high impedance leakage current (i leak ) 10 a output capacitance (c out ) 20 pf hdmi tmds differential pin capacitance 0.3 pf ac specifications intrapair (+ to ?) differential input skew for tmds clock rates up to 222.75 mhz 0.4 t bit ps intrapair (+ to ?) differential input skew for tmds clock rates above 222 .75 mhz 0.15 t bit + 112 ps channel - to - channel differential input skew 0.2 t p i xel + 1.78 ns tmds input clock range 25 225 mhz input clock jitter tolerance 0.5 0.25 t bit t bit 1 the following pins are 5 v tolerant: ddca_scl, ddca_sda, ddcb_scl, ddcb_sda, ddcc_scl, ddcc_sda, ddcd_scl, ddcd_sda, rx a _5v , rx b_5v , rx c _5v , rxd_5v , shared_edid, pwrdn , ep_miso.
data sheet adv7614 rev. c | page 5 of 20 data and i 2 c timing characteris tics dvdd = 1.8 v 5%, dvddio = 3 .3 v 5%, pvdd = 1.8 v 5%, tvdd = 3.3 v 5%, cvdd = 1.8 v 5%, t min to t max = ?40c to +70c, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ max unit video system clock and crystal crystal nominal frequency 24.576/28.6363 mhz crystal frequency stability 50 ppm llc frequency range 12.825 170 mhz external clock source 1 external crystal must operate at 1.8 v input high voltage v ih ball h15 (xtalp) driven with external clock source 1.2 v input low voltage v il ball h15 (xtalp) driven with ext ernal clock source 0.4 v reset feature reset pulse width 5 ms clock outputs llc mark space ratio t 9 :t 10 45:55 55:45 % duty cycle i 2 c ports (fast mode) xcl frequency 2 400 khz xcl mini mum pulse width high 2 t 1 600 ns xcl minimum pulse width low 2 t 2 1.3 s hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns xda setup time 2 t 5 100 ns xc l and xda rise time 2 t 6 300 ns xcl and xda fall time 2 t 7 300 ns setup time (stop condition) t 8 0.6 s i 2 c ports (normal mode) xcl frequency 2 100 khz xc l minimum pulse width high 2 t 1 4.0 s xcl minimum pulse width low 2 t 2 4.7 s hold time (start condition) t 3 4.0 s setup time (start condition) t 4 4.7 s xda setup time 2 t 5 250 ns xcl and xda rise time 2 t 6 1000 ns xcl and xda fall time 2 t 7 300 ns setup time (stop condition) t 8 4.0 s data and control outputs 3 data output transition time sdr (cp) t 11 end of valid data to negative clock edge 0.55 ns data output transition time sdr (cp) t 12 negative clock edge to start of valid data 1.0 ns video i 2 s port master mode sclk mark s pace ratio t 13 :t 14 45:55 55:45 % duty cycle lrclk data transition time t 15 end of valid data to negative sclk edge 10 ns lrclk data transition time t 16 negative sclk edge to start of valid data 10 ns i2sx data transition time 4 t 17 end of valid dat a to negative sclk edge 5 ns i2sx data transition time 4 t 18 negative sclk edge to start of valid data 5 ns 1 the xtal _ ctrl bit must be enabled f or external oscillator operation . a 1.8 v oscillator must be used. 2 the prefix x refers to s, ddca_s, ddcb_s, ddcc_s, and ddcd_s. 3 llc dll disabled. 4 the suffix x refers to 0, 1, 2, and 3.
adv7614 data sheet rev. c | page 6 of 20 power specifications dvdd = 1.8 v 5%, dvddio = 3.3 v 5%, pvdd = 1. 8 v 5%, tvdd = 3.3 v 5%, cvdd = 1.8 v 5%, t min to t max = ?40c to +70c, unless otherwise noted. table 3. parameter min typ max unit test conditions/comments power supplies digital core power supply (dvdd) 1.71 1.8 1.89 v digital i/o power supply (dvddio) 3.14 3.3 3.46 v pll power supply (pvdd) 1.71 1.8 1.89 v terminator power supply (tvdd) 3.14 3.3 3.46 v comparator power supply (cvdd) 1.71 1.8 1.89 v current consumption 1, 2, 3, 4 comparator power supply (i cvdd ) 102.9 121.9 ma 1080p 12-bit deep color with 4-channel pcm 3.7 4.0 ma power-down mode 0 digital core power supply (i dvdd ) 212.4 290.2 ma 1080p 12-bit deep color with 4-channel pcm 2.3 2.5 ma power-down mode 0 digital i/o power supply (i dvddio ) 29.7 167.0 ma 1080p 12-bit deep color with 4-channel pcm 1.3 1.4 ma power-down mode 0 pll power supply (i pvdd ) 74.7 87.5 ma 1080p 12-bit deep color with 4-channel pcm 0.2 0.22 ma power-down mode 0 termination power supply (i tvdd ) 185.3 204.5 ma 1080p 12-bit deep color with 4-channel pcm 1.1 1.2 ma power-down mode 0 1 all maximum current values are guaranteed by charac terization to assist in power supply design. 2 typical current consumption values are recorded with nominal voltage supply levels and a smptebar pattern. 3 maximum current consumption values are recorded with maximum rated voltage supply levels and a moire x pattern. 4 termination power supply includ es tvdd current consumed off chip. timing diagrams xda xcl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 notes 1. the prefix x refers to s, ddca_s, ddcb_s, ddcc_s, and ddcd_s. 08186-002 figure 2. i 2 c timing t 9 llc p0 to p35, vs, hs, de t 11 t 12 t 10 08186-003 figure 3. pixel port and control sdr output timing
data sheet adv7614 rev. c | page 7 of 20 sclk lrclk i2sx left-justified mode i2sx right-justified mode i2sx i 2 s mode msb msb ? 1 t 13 t 14 t 15 t 17 t 18 t 16 msb msb ? 1 lsb msb t 17 t 18 t 17 t 18 notes 1. the suffix x refers to 0, 1, 2, and 3. 08186-004 figure 4. i 2 s timing
adv7614 data sheet rev. c | page 8 of 20 absolute maximum rat ings table 4. parameter rating dvdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v cvdd to gnd 2.2 v tvdd to gnd 4.0 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v 5 v to leran t digital inputs to gnd 1 5.3 v digital output voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v xtal pins ?0.3 v to pvdd to 0.3 v maximum junction temperature (t j max ) 125c storage temperature 150c infrared reflow soldering (20 sec) 260c 1 the following inputs are 3.3 v inputs but are 5 v tolerant : ddca_scl, ddca_sda, ddcb_scl, ddcb_sda, ddcc_scl, ddcc_sda, ddcd_scl, ddcd_sda, rxa_5v, rxb_5v, rxc_5v, rxd_5v, shared_edid, pwrdn , ep_miso. stresses above those listed under absolute maximum ratings may cause permanent damage to the d evice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended peri ods may affect device reliability. package thermal perf ormance to reduce power consumption when using the adv7614 , the user is advised to turn off unused sections of the part. due to printed circuit board ( pcb ) metal variation and, thus, variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature bec ause this eliminates the variance associated with the ja val ue. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test ( dut ): t j = t s + ( jt w total ) where: t s is the package surface temperature (c). jt = 0.3c/w for a 260 - ball csp_ bga. w total = (( pvdd i pvdd ) + (0.05 t v dd i tvdd ) + ( cv dd i cv dd ) + ( dvdd i dvdd ) + ( dvddio i dvddio )). note that for w t o ta l , 5% of tvdd power is d issipated on the part itself. esd caution
data sheet adv7614 rev. c | page 9 of 20 p in configuration and function description s 08186-005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a b c d e f g h j k l m n p r t u v a b c d e f g h j k l m n p r t u v gnd rxd_2? rxd_1? rxd_0? rxd_c? gnd rxc_2? rxc_1? rxc_0? rxc_c? tvdd rxb_2? rxb_1? rxb_0? rxb_c? tvdd tvdd gnd rxd_5v rxd_2+ rxd_1+ rxd_0+ rxd_c+ tvdd rxc_2+ rxc_1+ rxc_0+ rxc_c+ tvdd rxb_2+ rxb_1+ rxb_0+ rxb_c+ tvdd rxa_2+ rxa_2? tvdd tvdd cvdd gnd tvdd tvdd gnd gnd gnd tvdd tvdd gnd gnd gnd gnd rxa_1+ rxa_1? rxc_5v rxb_5v rxa_5v ddcd_ sda ddcd_ scl ddcc_ sda ddcc_ scl cvdd gnd rterm cvdd ddcb_ sda ddcb_ scl ddca_ scl ddca_ sda tvdd rxa_0+ rxa_0? de cec nc nc nc nc gnd gnd rxa_c+ rxa_c? hs vs_ field ep_miso ep_mosi gnd cvdd tvdd gnd p1 p0 ep_cs ep_sck gnd gnd gnd gnd pvdd pvdd test1 test2 p3 p2 nc nc = no connect. do not conenct to this pin. nc gnd gnd gnd gnd gnd gnd xtalp pvdd nc nc gnd gnd mclk out spdif/ dsd0a/ dst dvdd gnd gnd gnd gnd gnd xtaln pvdd gnd gnd p4 p5 lrclk/ dsd2b/ dst_ff sclk/ dst_clk dvdd dvdd gnd gnd gnd pvdd pvdd pvdd nc nc p6 p7 i 2 s3/ dsd2a/ hbr3 i 2 s2/ dsd1b/ hbr2 dvdd dvdd gnd gnd gnd pvdd nc nc nc nc p8 gnd gnd gnd dvdd dvdd gnd gnd gnd pvdd nc nc gnd gnd p9 dvddio dvddio dvddio nc nc nc nc p10 p11 i 2 s0/ dsd0b/ hbr0 i 2 s1/ dsd1a/ hbr1 pvdd pvdd nc nc p12 p13 gnd gnd scl dvddio int1 nc dvddio gnd nc shared_ edid nc gnd nc nc gnd gnd p14 p15 gnd gnd p25 dvddio sda int2 dvddio gnd reset nc nc gnd nc nc nc nc p16 p17 p19 p21 p23 gnd p26 test3 p28 gnd p31 p33 p35 gnd nc pvdd pvdd nc gnd p18 p20 p22 p24 gnd p27 llc p29 gnd p30 p32 p34 gnd nc nc nc gnd pwrdn figure 5. pin configuration table 5 . pin function descriptions pin no. mnemonic type description a1 gnd gro und ground. a2 rxd_2? hdmi input digital input channel 2 complement of port d in the hdmi interface . a3 rxd_1? hdmi input digital input channel 1 complement of port d in the hdmi interface . a4 rxd_0? hdmi input digital input channel 0 complement of port d in the hdmi i nterface . a5 rxd_c? hdmi input digital input clock complement of port d in the hdmi interface . a6 gnd ground ground. a7 rxc_2? hdmi input digital input channel 2 complement of port c in the hdmi interface . a8 rxc_1? hdmi input digital input channel 1 c omplement of port c in the hdmi interface . a9 rxc_0? hdmi input digital input channel 0 complement of port c in the hdmi interface . a10 rxc_c? hdmi input digital input clock complemen t of port c in the hdmi interface . a11 tvdd power terminator supply vo ltage (3.3 v ). a12 rxb_2? hdmi input digital input channel 2 complement of port b in the hdmi interface .
adv7614 data sheet rev. c | page 10 of 20 pin no. mnemonic type description a13 rxb_1? hdmi input digital input channel 1 complement of port b in the hdmi interface . a14 rxb_0? hdmi input digital input channel 0 complement o f port b in the hdmi interface . a15 rxb_c? hdmi input digital input clock complement of port b in the hdmi interface . a16 tvdd power terminator supply voltage (3.3 v). a17 tvdd power terminator supply voltage (3.3 v). a18 gnd ground ground. b1 rxd_5v hdmi input 5 v detect pin for port d in the hdmi interface . b2 rxd_2+ hdmi input digital input channel 2 tru e of port d in the hdmi interface . b3 rxd_1+ hdmi input digital input channel 1 tru e of port d in the hdmi interface . b4 rxd_0+ hdmi input digita l input channel 0 tru e of port d in the hdmi interface . b5 rxd_c+ hdmi input digital input clo ck tru e of port d in the hdmi interface . b6 tvdd power terminator supply voltage (3.3 v). b7 rxc_2+ hdmi input digital input channel 2 tru e of port c in the hd mi interface . b8 rxc_1+ hdmi input digital input channel 1 tru e of port c in the hdmi interface . b9 rxc_0+ hdmi input digital input channel 0 tru e of port c in the hdmi interface . b10 rxc_c+ hdmi input digital input clo ck tru e of port c in the hdmi inte rface . b11 tvdd power terminator supply voltage (3.3 v). b12 rxb_2+ hdmi input digital input channel 2 tru e of port b in the hdmi interface . b13 rx b _1+ hdmi input digital input channel 1 tru e of port b in the hdmi interface . b14 rxb_0+ hdmi input digit al input channel 0 tru e of port b in the hdmi interface . b15 rxb_c+ hdmi input digital input clo ck tru e of port b in the hdmi interface . b16 tvdd power terminator supply voltage (3.3 v). b17 rxa_2+ hdmi input digital input channel 2 tru e of port a in th e hdmi interface . b18 rxa_2? hdmi input digital input channel 2 complement of port a in the hdmi interface . c1 pwrdn digital i nput active low system power detect . if low, edid can be powered from a 5 v signal of the hdmi port when connected to active equipmen t. c2 tvdd power terminator supply voltage (3.3 v ). c3 tvdd power terminator supply voltage (3.3 v ). c4 cvdd power comparator supply voltage (1.8 v). c5 gnd ground ground. c6 tvdd power terminator supply voltage (3.3 v). c7 tvdd power terminator supp ly voltage (3.3 v ). c8 gnd ground ground. c9 gnd ground ground. c10 gnd ground ground. c11 tvdd power terminator supply voltage (3.3 v). c12 tvdd power terminator supply voltage (3.3 v) . c13 gnd ground ground. c14 gnd ground ground. c15 gnd ground ground. c16 gnd ground ground. c17 rxa_1+ hdmi input digital input channel 1 tru e of port a in the hdmi interface. c18 rxa_1? hdmi input digital input channel 1 complement of port a in the hdmi interface. d1 rxc_5v hdmi input 5 v detect pin for port c in the hdmi interface . d2 rxb_5v hdmi input 5 v detect pin for port b in the hdmi interface . d3 rxa_5v hdmi input 5 v detect pin for port a in the hdmi interface . d4 ddcd_sda hdmi input hdcp slave serial data port d. ddcd_sda is a 3.3 v input that is 5 v tolerant. d5 ddcd_scl hdmi input hdcp slave serial clock port d. ddcd_scl is a 3.3 v input that is 5 v tolerant. d6 ddcc_sda hdmi input hdcp slave serial data port c. ddcc_sda is a 3.3 v input that is 5 v tolerant. d7 ddcc_scl hdmi input hdcp slave se rial clock port c. ddcc_scl is a 3.3 v input that is 5 v tolerant. d8 cvdd power comparator supply voltage (1.8 v). d9 gnd ground ground. d10 rterm misc ellaneous analog this pin s ets internal termination resistance. use a 500 resistor between this pin and gnd.
data sheet adv7614 rev. c | page 11 of 20 pin no. mnemonic type description d11 cvdd power comparator supply voltage (1.8 v). d12 ddcb_sda hdmi input hdcp slave serial data port b. ddcb_sda is a 3.3 v input that is 5 v tolerant. d13 ddcb_scl hdmi input hdcp slave serial clock port b. ddcb_scl is a 3.3 v input that is 5 v tolerant. d14 ddca_scl hdmi input hdcp slave serial clock port a. ddca_scl is a 3.3 v input that is 5 v tolerant. d15 ddca_sda hdmi input hdcp slave serial data port a. ddca_sda is a 3.3 v input that is 5 v tolerant. d16 tvdd power terminator supply voltage (3.3 v ). d17 rxa_0+ hdmi input digital input channel 0 tru e of port a in the hdmi interface . d18 rxa_0? hdmi input digital input channel 0 complement of port a in the hdmi interface . e1 de digital video output data enable. de is a signal that indicates active pixel data. e2 cec digital i/o consumer electronic control channel. e3 nc no connect do not connect. e4 nc no connect do not connect. e15 gnd ground ground. e16 gnd ground ground. e17 rxa_c+ hdmi input digital input clock tru e of por t a in the hdmi interface. e18 rxa_c? hdmi input digital input clock complement of port a in the hdmi interface. f1 hs digital video output horizontal synchronization output signal in the hdmi processor . f2 vs_field digital video output vs is a vertical synchronization output signal i n the hdmi processor. field is a field synchronization output signal in all interlaced video modes. vs or field can be configured for this pin. f3 ep_miso digital input spi master in put /slave out put for external edid interface. f4 ep_mosi digital output spi master output/slave input for external edid interface. f15 gnd ground ground. f16 cvdd power comparator supply voltage (1.8 v). f17 tvdd power terminator supply voltage (3.3 v). f18 gnd ground ground. g1 p1 digital video output video pixel output port. g2 p0 digital video output video pixel output port. g3 ep_cs digital output spi chip select for external edid interface. g4 ep_sck digital output spi clock for external edid interface. g7 gnd ground ground. g8 gnd ground ground. g9 gnd ground g round. g10 gnd ground ground. g11 pvdd power pll supply voltage (1.8 v). g12 pvdd power pll supply voltage (1.8 v). g15 nc no connect do not connect. g16 nc no connect do not connect. g17 test1 tes t connect to gnd through a 10 k resistor. g18 test2 tes t connect to gnd through a 10 k resistor. h1 p3 digital video output video pixel output port. h2 p2 digital video output video pixel output port. h3 nc no connect do not connect. h4 nc no connect do not connect. h7 gnd ground ground. h8 gnd ground ground. h9 gnd ground ground. h10 gnd ground ground. h11 gnd ground ground. h12 gnd ground ground. h15 xtal p misc ellaneous a nalog this is the in put pin for the 28.6363 mhz crystal , or it can be ove rdrive n by an external 1.8 v, 28.6363 mhz clock oscillator source to clock the adv7614 . a crystal frequency of 2 4 .576 mhz is also supported. h16 pvdd power pll supply voltage (1.8 v).
adv7614 data sheet rev. c | page 12 of 20 pin no. mnemonic type description h17 nc no connect do not connect. h18 nc no connect do not connect. j1 gnd ground ground. j2 gnd ground ground. j3 mclkout digital output audio master clock output. j4 s/ pdif/dsd0a/dst digital output s/pdif digital audio output ( s/pdif ). first dsd data c hannel (dsd0a). dst stream (dst). j7 dvdd power digital supply voltage (1.8 v). j8 gnd ground ground. j9 gnd ground ground. j10 gnd ground ground. j11 gnd ground ground. j12 gnd ground ground. j15 xtal n misc ellaneous analog this pin should be co nnected to the 28.6363 mhz crystal or left as a no connect pin if an external 1.8 v, 28.6363 mhz clock oscillator source is used to clock the adv7614 . in crystal mode, the crystal must be a fun damental crystal. a crystal frequency of 24.576 mhz is also supported. j16 pvdd power pll supply voltage (1.8 v). j17 gnd ground ground. j18 gnd ground ground. k1 p4 digital video output video pixel output port. k2 p5 digital video output video pixel output port. k3 lrclk/dsd2b/dst_ff digital output data output clock. left and right audio channels (lrclk) . sixth dsd data channel (dsd2b). dst frame (dst_ff). k4 sclk/dst_clk digital output audio serial clock output (sclk) . dst clock (dst_cl k). k7 dvdd power digital supply voltage (1.8 v). k8 dvdd power digital supply voltage (1.8 v). k9 gnd ground ground. k10 gnd ground ground. k11 gnd ground ground. k12 pvdd power pll supply voltage (1.8 v). k15 pvdd power pll supply voltage (1.8 v). k16 pvdd power pll supply voltage (1.8 v). k17 nc no connect do not connect. k18 nc no connect do not connect. l1 p6 digital video output video pixel output port. l2 p7 digital video output video pixel output port. l3 i 2 s3/dsd2a/hbr3 digital output i 2 s audio (channel 7 and channel 8) (i 2 s3) . fifth dsd data channel (dsd2a). fourth block of hbr stream (hbr3). l4 i 2 s2/dsd1b/hbr2 digital output i 2 s audio (channel 5 and channel 6) (i 2 s2) . fourth dsd data channel (dsd1b). third block of hb r stream (hbr2). l7 dvdd power digital supply voltage (1.8 v). l8 dvdd power digital supply voltage (1.8 v). l9 gnd ground ground. l10 gnd ground ground. l11 gnd ground ground. l12 pvdd power pll supply voltage (1.8 v). l15 nc no connect do not conn ect. l16 nc no connect do not connect.
data sheet adv7614 rev. c | page 13 of 20 pin no. mnemonic type description l17 nc no connect do not connect. l18 nc no connect do not connect. m1 p8 digital video output video pixel output port. m2 gnd ground ground. m3 gnd ground ground. m4 gnd ground ground. m7 dvdd power digital s upply voltage (1.8 v). m8 dvdd power digital supply voltage (1.8 v). m9 gnd ground ground. m10 gnd ground ground. m11 gnd ground ground. m12 pvdd power pll supply voltage (1.8 v). m15 nc no connect do not connect. m16 nc no connect do not connect. m17 gnd ground ground. m18 gnd ground ground. n1 p9 digital video output video pixel output port. n2 dvddio power digital i/o supply voltage (3.3 v). n3 dvddio power digital i/o supply voltage (3.3 v). n4 dvddio power digital i/o supply voltage (3.3 v ). n15 nc no connect do not connect. n16 nc no connect do not connect. n17 nc no connect do not connect. n18 nc no connect do not connect. p1 p10 digital video output video pixel output port. p2 p11 digital video output video pixel output port. p3 i 2 s0/dsd0b/hbr0 digital output i 2 s audio (channel 1 and channel 2) (i 2 s0) . second dsd data channel (dsd0b). first block of hbr stream (hbr0). p4 i 2 s1/dsd1a/hbr1 digital output i 2 s audio (channel 3 and channel 4) (i 2 s1) . third dsd data channel ( dsd1a). second block of hbr stream (hbr1). p15 pvdd power pll supply voltage (1.8 v). p16 pvdd power pll supply voltage (1.8 v). p17 nc no connect do not connect. p18 nc no connect do not connect. r1 p12 digital video output video pixel output por t. r2 p13 digital video output video pixel output port. r3 gnd ground ground. r4 gnd ground ground. r5 scl digital i/o i 2 c port serial clock input. the maximum clock rate is 400 khz. scl is the clock line for the control port. r6 dvddio power digital i/o supply voltage (3.3 v). r7 int1 digital output interr upt pin 1. this pin can be active low or active high. when status bits chang e, this pin is triggered. the events that trigger an interrupt are under user control. r8 nc no connect do not connect. r9 dvddio power digital i/o supply voltage (3.3 v). r10 gnd ground ground. r11 nc no connect do not connect. r12 shared_edid digital input edid flag. when high, all four hdmi ports share a common edid. when low, port d does not share a common edid ; port d operates with a separate edid. r13 nc no connect do not connect. r14 gnd ground ground. r15 nc no connect do not connect.
adv7614 data sheet rev. c | page 14 of 20 pin no. mnemonic type description r16 nc no connect do not connect. r17 gnd ground ground. r18 gnd ground ground. t1 p14 digital video output video pixel outp ut port. t2 p15 digital video output video pixel output port. t3 gnd ground ground. t4 gnd ground ground. t5 p25 digital video output video pixel output port. t6 dvddio power digital i/o supply voltage (3.3 v). t7 sda digital i/o i 2 c port serial data input/output pin. sda is the data line for the control port. t8 int2 digital output inte rrupt pin 2. this pin can be active low or active high. when status bits cha n g e, this pin is triggered. the events that trigger an interrupt are under user control. t9 dvddio power digital i/o supply voltage (3.3 v). t10 gnd ground ground. t11 reset digital input chip reset. active low. the minimum low time for a reset to take place is 5 ms. t12 nc no connect do not connect. t13 nc no connect do not connect. t14 gnd ground ground. t15 nc no connect do not connect. t16 nc no connect do not connect. t17 nc no connect do not connect. t18 nc no connect do not connect. u1 p16 digital video output video pixel output port. u2 p17 digital video out put video pixel output port. u3 p19 digital video output video pixel output port. u4 p21 digital video output video pixel output port. u5 p23 digital video output video pixel output port. u6 gnd ground ground. u7 p26 digital video output video pixel o utput port. u8 test3 tes t co n n ect to gnd through a 10 k r esistor. u9 p28 digital video output video pixel output port. u10 gnd ground ground. u11 p31 digital video output video pixel output port. u12 p33 digital video output video pixel output port. u13 p35 digital video output video pixel output port. u14 gnd ground ground. u15 nc no connect do not connect. u16 pvdd power pll supply voltage (1.8 v). u17 pvdd power pll supply voltage (1.8 v). u18 nc no connect do not connect. v1 gnd ground grou nd. v2 p18 digital video output video pixel output port. v3 p20 digital video output video pixel output port. v4 p22 digital video output video pixel output port. v5 p24 digital video output video pixel output port. v6 gnd ground ground. v7 p27 digit al video output video pixel output port. v8 llc digital video output line - locked output clock for the pixel data ( range i s 13.5 mhz to 170 mhz). v9 p29 digital video output video pixel output port. v10 gnd ground ground. v11 p30 digital video output v ideo pixel output port. v12 p32 digital video output video pixel output port. v13 p34 digital video output video pixel output port.
data sheet adv7614 rev. c | page 15 of 20 pin no. mnemonic type description v14 gnd ground ground. v15 nc no connect do not connect. v16 nc no connect do not connect. v17 nc no connect do not co nnect. v18 gnd ground ground.
adv7614 data sheet rev. c | page 16 of 20 functional overview hdmi receiver the hdmi receiver on the adv7614 incorporates active equalization of the hdmi data signals. this equalization compensates fo r the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies. the equalization is programmable. it is capable of equalizing for cable lengths up to 30 m eters to achieve robust receiver performance at even the highest hdmi data rates. the hdmi receiver supports all hdtv formats up to 1080p and all display resolutions up to uxga (1600 1200 at 60 hz). with the inclusion of hdcp, displays can receive encrypted video co nte nt. the hdm i interface o f the adv7614 allows for authen - tication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during trans mis - sion as specified by the hdcp 1.3 protocol. the hdmi receiver offers advanced audio functionality. it sup - ports multichannel i 2 s audio for up to eight channe ls. it also supports a six - dsd channel interface with each channel carrying an over sample d 1 - bi t representation of the audio signal as delivered on sacd. it incorporates a dst interface that outputs audio data decoded from dst audio packets. the adv7614 can also receive hbr audio packet streams and outputs them through the hbr interface in an s / pdif format conforming to the iec60958 standard. it supports multichannel i 2 s audio for up to eight channels. the receiver also con tains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. on detection of these conditions, the audio data can be ramped to prevent audio clicks or pops. component processor (cp) the video standards supported by the cp are 525i, 625i, 525p, 625 p, 720p, 1080i, 1080p, 1250i, vga up to uxga at 60 hz, and many other standards. automatic adjustments within the cp include gain (contrast) and offset (brightness); manual adjustment controls are also supported. a fully programmable any - to - any 3 3 colo r space conversion (csc) matrix is placed between the hdmi processor and the cp section. this enables ycrcb - to - rgb and ycrcb - to - rgb conversions. many other standards of color space can be implemented using the color space converter. cp pixel data output m odes the output section of the cp is highly flexible. it can be confi - gured in an sdr mode with one data packet per clock cycle or in a ddr mode where data is presented on the rising and falling edge of the clock. in sdr mode, a 16 - /20 - /24 - bit 4:2:2 or 24 - /30 - /36 - bit 4:4:4 output is possible. in these modes, the hs, vs , field, and de (where applicable) timing reference signals are provided. in ddr mode, the adv7614 can be configured in an 8 - /10 - /12 - bit 4 :2:2 ycrcb or 12 - bit 4:4:4 rgb/ ycrcb pixel output interface with corresponding timing signals. i 2 c interface the adv7614 supports a 2 - wire serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. the adv7614 is controlled by an external i 2 c master device, such as a micro controller. other features in addition to hs, vs, and field output signals with progr amma - ble position, polarity, and width, the adv7614 provides the following: ? programmabl e interrupt request output pins: in t1 a nd in t2 ? low power consumption: 1.8 v digital core, 3.3 v d igital in put /output, low power power - down mode, and green pc mode ? 15 mm 15 mm, rohs - compliant bga package for more detailed product information about the adv7614 , contact a local analog devices, inc. , sales office .
data sheet adv7614 rev. c | page 17 of 20 outline dimensions a b c d e f g 9 8 11 10 13 12 7 6 5 4 2 3 1 13.60 bsc sq h j k l m n p r t u v 0.35 nom 0.30 min 15.10 15.00 sq 14.90 1.50 1.36 1.21 1.11 1.01 0.91 15 14 17 1618 compliant to jedec standards mo-275-kkaa-1. 1 1-22-20 1 1- a 0.50 0.45 0.40 coplanarit y 0.12 ball diameter 0.80 bsc de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane figure 6. 260 - ball chip scale package ball grid array [csp_bga] (bc - 260 - 1) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option adv 7614 bbcz ?4 0c to +70c 260- ball chi p sca le pa ck ag e ball grid array [csp_ bga] bc - 260 -1 eval - adv7614eb1z ADV7614BBCZ fro nt - end evaluation board 1 z = rohs compliant part. 2 th e ADV7614BBCZ is programmed with internal hdc p keys. customers must have hdcp adopter status (consult digital content protection , llc , for licensing requirements) to purchase any components with internal hdcp keys.
adv7614 data sheet rev. c | page 18 of 20 notes
data sheet adv7614 rev. c | page 19 of 20 notes
adv7614 data sheet rev. c | page 20 of 20 notes i 2 c refers to a communications protocol originally developed b y phillips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high - definition multimedia interface are trademarks or registered trademarks of hdmi licensing llc in the united states and other countries. ? 201 3 analog devices, i nc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 0 8186 -0- 9 /13(c)

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